This invention generally relates to the formation of metal filled semiconductor features and more particularly to a method for forming metal filled semiconductor features to improve a subsequent metal CMP process to avoid CMP underpolishing or CMP overpolishing.
Multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects providing electrical interconnection between various portions of a semiconductor device that form the basis of this technology require increasingly complicated manufacturing processes to avoid new problems engendered by the adoption of new manufacturing processes driven by the goals of reliability, low resistance and low capacitance electrical properties, and structurally stable semiconductor features. Many of the interconnect features include high aspect ratio apertures, including contact holes, vias, metal interconnect lines (trench lines) and other features. Also included are features having larger dimensions including trench lines and bonding pads. Reliable formation of these interconnect features including structural stability when exposed to various processing steps is critical to the formation of reliable semiconductor devices.
Copper and copper alloys have become the metal of choice for forming many interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities including increased device speed.
Electroplating (electrodeposition) or electroless plating, particularly with respect to copper containing semiconductor features are being established as preferable methods for filling semiconductor device metal interconnect features to form structures including vias trench lines, and bonding pads. Typically, electroplating uses a suspension of positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate, as a source of electrons, to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer and within etched features to provide an electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface is electroplated with an appropriate metal, for example, aluminum or copper.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically including a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects (trench lines) to electrically interconnect areas within the multilayer device and bonding pads to interconnect the various devices on the chip surface or to interconnect the device to a semiconductor packaging frame. For example, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi layer device. Metal interconnect lines (trench lines) typically serve to selectively interconnect conductive regions within a layer of a multilayer device.
In forming a typical metal interconnect feature, feature openings are etched into one or more insulating layers and are back-filled with metal, for example copper. The insulating layers (IMD layers) are typically a low-k (low dielectric constant) insulating material which reduces signal delay times caused by parasitic capacitance. The process by which feature openings are selectively etched into the insulating layers is typically a photolithographic patterning process, followed by a reactive ion etch (RIE) process, both of which are commonly known in the art.
In filling the semiconductor feature openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of etched features. The method generally includes first depositing a barrier/adhesion layer, for example, tantalum nitride over the etched feature opening surfaces, depositing a metal seed layer, for example copper, over the barrier/adhesion layer by physical vapor deposition (PVD) or chemical vapor deposition (CVD), followed by electroplating a metal, for example copper, over the seed layer to fill the etched features. The excess electroplated copper overlying the features is then removed according to a planarization process, for example, by chemical mechanical polishing (CMP), to define an electrically conductive interconnect feature.
One problem with the prior art metal filled semiconductor feature formation process, for example including copper filled features, includes the copper CMP planarization process which is carried out subsequent to copper filling the semiconductor feature, for example by electroplating. During a typical copper CMP process the excess copper overlying an IMD layer including a dielectric anti-reflectance coating (DARC), for example silicon oxynitride, and a barrier/adhesion layer, for example tantalum nitride, are removed. During the process, due to the relatively thin layers and high polishing rate (material removal rate) of the DARC layer and barrier/adhesion layer, for example, about 1000 Angstroms/min, it is frequently difficult to control the endpoint in the CMP process and therefore to control the final thickness of the copper filled semiconductor feature. In competing processing goals, it is important to completely remove the dielectric layers, for example, the DARC layer and the barrier adhesion layer overlying the IMD layer to reduce contributions to overall capacitance in a multi-level device while avoiding overpolishing to ensure the manufacture of metal filled semiconductor features within design specifications.
For example, in an exemplary damascene structure manufacturing process according to the prior art, referring to FIG. 1A is shown a portion of a multi-level semiconductor device including a dielectric insulating layer 12, also referred to as inter-metal dielectric (IMD) layer, for example, having dielectric constant less than about 3.0, for example fluorinated silica glass (FSG). Overlying the IMD layer, a DARC layer 16, formed of, for example, silicon oxynitride (SiON), is typically formed over the IMD layer 12 to reduce undesired light reflections in a subsequent photolithographic patterning process to define a feature opening for anisotropic etching.
Referring to FIG. 1B, feature opening 14 is anisotropically etched following photolithographic patterning of an overlying photoresist layer (not shown) the feature opening being etched through a thickness of the DARC layer 16 overlying the IMD layer 12, to typically form closed communication with an underlying conductive area (not shown). Following anisotropic etching and removal of the photoresist layer (not shown) by a wet or dry ashing process, a barrier/adhesion layer 18, typically a refractory metal nitride such as tantalum nitride, is typically conformally deposited to line the feature opening 14 to prevent copper diffusion of subsequently electroplated copper into the IMD layer 12 to thereby undesirably alter the insulating characteristics of IMD layer 12.
Referring to FIG. 1C a copper layer 19 is typically electroplated onto a copper seed layer (not shown) deposited over the barrier/adhesion layer 18 to provide an electrical potential source for inducing electroplating of copper out of an electrolyte solution. Referring to FIGS. 1D or 1E, is shown the remaining metal filled semiconductor feature after carrying out a copper CMP process where, for example, the Cu CMP process underpolishes (FIG. 1D) by not entirely removing the DARC layer 16, and the barrier/adhesion layer 18 or overpolishes (FIG. 1E) by completely removing DARC layer 16, and the barrier/adhesion layer 18 including a portion of the IMD layer 12. Due to the relatively high polishing rates (e.g., greater than 500 Angstrom/min) of the DARC layer 16 and the barrier/adhesion layer 18, endpoint control of the Cu CMP polishing process is difficult to achieve, resulting in either underpolishing (e.g., FIG. 1D) by leaving remaining unpolished portions of DARC layer 16 and barrier/adhesion layer 18 or overpolishing (e.g., FIG. 1E) by excessive removal of IMD layer 12 resulting in semiconductor feature thickness outside of design specification.
Therefore, there is a need in the semiconductor processing art to develop a method whereby metal filled semiconductor features may be formed to improve a subsequent chemical mechanical polishing step.
It is therefore an object of the invention to provide a method whereby metal filled semiconductor features may be formed to improve a subsequent chemical mechanical polishing step while overcoming other deficiencies and shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process.
In a first embodiment of the invention, the method includes providing a semiconductor processing surface having a anisotropically etched semiconductor feature formed through a thickness including a second dielectric insulating layer overlying a first dielectric insulating layer, the second dielectric insulating layer having a CMP material removal rate in a CMP process less than about xc2xd of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature with a metal to form a metal filled semiconductor feature; and, planarizing according to the CMP process excess material including the metal overlying the second dielectric insulating layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.